1. Field of the Invention
The present invention relates to a counter employed in a pulse phase difference encoding circuit, time to digital conversion circuit, etc., or a synchronous counter employed in a clock-controlled PLL and the like. In particular, the invention concerns a synchronous counter intended to enable performance of higher-speed clock operations and multi-bit arrangements.
2. Related Arts
While a level-inversion counter has a circuit which is adapted to input a clock signal having a given frequency value and count the number of periodic cycles of this clock signal in order to output the-same, as examples of such a type of counter, the convention counter circuit shown in FIG. 13 and the conventional counter circuit shown in FIG. 14 are publicly known.
The counter circuit shown in FIG. 13 is a counter circuit in which more multi-input AND circuits are connected as the bit order increases from a lower bit-order toward a higher bit-order. This counter circuit is designed such that output signals of logic circuits for producing logical products of output signals from preceding flip-flop circuits are supplied to flip-flop circuits Q1 to Q15. This counter circuit, however, has a drawback in that although it theoretically operates at maximum speed, an increase in the number of bits used causes an exponential increase in the number of transistor elements necessary to form the relevant logic circuits. This results in the necessity of using a significantly large element area, while the wiring also becomes very complicated, rendering the counter circuit impractical.
The counter circuit shown in FIG. 14 is a counter circuit in which the number of within-circuit elements and the amount of wiring are reduced over the counter circuit shown in FIG. 13. In this counter circuit, AND circuits are connected in series in order to reduce the number of elements and the amount of wiring. In this type of synchronous counter, however, since the output signals from carrying gate circuits within the counter are serially arranged and sequentially transferred to their upper-order bit elements, with the result that the time delays of the signals accumulate, it happens in some cases that the counter is operated by a higher-speed clock signal and erroneous operations occur due to the accumulation of the above-mentioned time delays. For this reason, this synchronous counter has a problem in that when it is used with a multi-bit element arrangement, acceleration of the operations thereof cannot be satisfactorily realized.
Under the above-mentioned circumstances, development of a synchronous counter capable of simultaneously solving the two above-mentioned problems, i.e., a synchronous counter compatible with accelerated operation and reduction of the circuit area has hitherto been in demand.
As such a synchronous counter, proposed in view of the above-mentioned problems, a counter such as that disclosed in, for example, Published Unexamined Japanese Patent Application No. 62-217722 has been known. FIGS. 15 through 17 are views showing the circuit of the above publication. The counter circuit shown in FIG. 15 is one in which the output Q0 of the (0)th bit flip-flop circuit that is most frequently inverted is commonly inputted to each of the flip-flop circuits, thereby realizing high-speed operation compared to the circuit shown in FIG. 14. Further, the counter circuit shown in FIG. 16 is one in which the output signal Q1 of the flip-flop circuit that is the next most frequently inverted, as well as the output signal Q0 of the (0)th bit flip-flop circuit, is commonly inputted to the succeeding flip-flop circuits, thereby realizing accelerated operation of the circuit. However, in cases where the relevant circuits are actually formed on a wiring board, wiring of two common wire lines with respect to each of the flip-flop circuits disadvantageously results in complication of the wiring pattern and a subsequent decrease in the degree of freedom of the wiring pattern. FIG. 17 shows a circuit which solves this problem and in which the two output signals Q0 and Q1 are combined into one common line.
The operation of the counter circuit shown in FIG. 15 will now be described with reference to the time chart shown in FIG. 18, explanation in this case being limited to the bit range from the count signal Q0 to the count signal Q7 and a state where the counter exhibits greatest variation, namely where each and every bit involved exhibits variation. The time when the count signal Q7, which is an upper-order bit count signal, changes in FIG. 15 corresponds to the timing with which the clock signal CK has changed from a LOW state (logical value 0) to a HIGH state during a time period in which each of the count signals Q0 to Q6 is in a HIGH state (logical value 1). Explanation will begin from a point corresponding to a state (wherein the count signal Q1 is in a LOW state and all the count signals Q2 to Q6 are in HIGH states) preceding by two clock pulses the state wherein all the count signals Q0 to Q6 are in HIGH states. When in FIG. 15 the clock signal CK changes from LOW state to HIGH state as indicated in the time chart of FIG. 18, the count signal Q0 changes to LOW state and the count signal Q1 changes to HIGH state. As a result, the input signals of the element represented by the numeral 14 both change to HIGH state and the output signals thereof change to HIGH state. Similarly, since the input signals of the element represented by the numeral 16 both change to HIGH state, the output signals thereof also change to HIGH state. As mentioned above, the output signals of the elements 14, 16, 18, 20, and 22 change to HIGH state while they are delayed sequentially from the lower-order bit side. The circuit show in FIG. 15 achieves a reduction in the number of elements employed by utilizing the above-mentioned structure.
However, while the synchronous counter disclosed in Japanese Patent Unexamined Publication No. 62-217722 frequently inverts the lower-order bit count signals Q0 and Q1, which cause production of time delays, and commonly input them to succeeding flip-flop circuits by providing common lines thereto, thereby realizing a higher-speed operation than in the prior art, any specific change other than in the case of the synchronous counter of FIG. 14 does not basically occur with respect to such succeeding flip-flop circuits. Therefore, the synchronous counter disclosed above still has the problem that time delays accumulate. From the viewpoint in the above publication, in cases where higher-speed operation is desired, this results in the count signals being further commonly inputted sequentially from lower-order bit count signals. This disadvantageously raises such problems as, for example, complication of the wiring pattern, decrease in the degree of freedom of the wiring pattern, etc. Accordingly, in the synchronous counter disclosed in the above publication, there has been the problem that higher-speed operation, simplification of the wiring pattern, and reduction in the circuit area cannot be simultaneously satisfied.